xen/arm: SCTLR_EL1 is a 64-bit register on Arm64
authorJulien Grall <julien.grall@arm.com>
Tue, 23 Jul 2019 21:35:48 +0000 (22:35 +0100)
committerStefano Stabellini <sstabellini@kernel.org>
Mon, 28 Oct 2019 21:39:55 +0000 (14:39 -0700)
commit6eb3f767849fe5b3aadd75e7f88217313d024c95
tree4583fb81bef188993c72608f18627ecf17ed7f70
parentcb86f3d039fcb6afa7b6ee3738050e08b1e5b71a
xen/arm: SCTLR_EL1 is a 64-bit register on Arm64

On Arm64, system registers are always 64-bit including SCTLR_EL1.
However, Xen is assuming this is 32-bit because earlier revision of
Armv8 had the top 32-bit RES0 (see ARM DDI0595.b).

>From Armv8.5, some bits in [63:32] will be defined and allowed to be
modified by the guest. So we would effectively reset those bits to 0
after each context switch. This means the guest may not function
correctly afterwards.

Rather than resetting to 0 the bits [63:32], preserve them across
context switch.

Note that the corresponding register on Arm32 (i.e SCTLR) is always
32-bit. So we need to use register_t anywhere we deal the SCTLR{,_EL1}.

Outside interface is switched to use 64-bit to allow ABI compatibility
between 32-bit and 64-bit.

[Stefano: fix typo in commit message]

Signed-off-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Stefano Stabellini <stefanos@xilinx.com>
Reviewed-by: Volodymyr Babchuk <volodymyr.babchuk@epam.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
(cherry picked from commit e98edccb944a80db782e551f3090628e66c7fb52)
[backport: drop change to non-existing vcpu_has_cache_enabled]
tools/xentrace/xenctx.c
xen/arch/arm/guest_walk.c
xen/arch/arm/traps.c
xen/include/asm-arm/domain.h
xen/include/public/arch-arm.h